St-t UPSD3212C Manual do Utilizador

1/163December 2004uPSD3212A, uPSD3212CuPSD3212CVFlash Programmable System Devices with8032 MCU with USB and Programmable LogicFEATURES SUMMARY FAST 8

uPSD3212A, uPSD3212C, uPSD3212CV10/163Table 2. 80-Pin Package Pin DescriptionPort PinSignalNamePin No. In/OutFunctionBasic AlternateAD0 36 I/OExternal

uPSD3212A, uPSD3212C, uPSD3212CV100/163Erasing Flash MemoryFlash Bulk Erase. The Flash Bulk Erase instruc-tion uses six WRITE operations followed by a

101/163uPSD3212A, uPSD3212C, uPSD3212CVSpecific FeaturesFlash Memory Sector Protect. Each primaryand secondary Flash memory sector can be sepa-rately

uPSD3212A, uPSD3212C, uPSD3212CV102/163SRAMThe SRAM is enabled when SRAM Select (RS0)from the DPLD is High. SRAM Select (RS0) cancontain up to two pro

103/163uPSD3212A, uPSD3212C, uPSD3212CVMemory Select Configuration in Program andData Spaces. The MCU Core has separate ad-dress spaces for Program me

uPSD3212A, uPSD3212C, uPSD3212CV104/163Separate Space Mode. Program space is sepa-rated from Data space. For example, Program Se-lect Enable (PSEN) is

105/163uPSD3212A, uPSD3212C, uPSD3212CVPage RegisterThe 8-bit Page Register increases the addressingcapability of the MCU Core by a factor of up to 25

uPSD3212A, uPSD3212C, uPSD3212CV106/163PLDSThe PLDs bring programmable logic functionalityto the uPSD. After specifying the logic for thePLDs in PSDso

107/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 54. PLD DiagramNote: 1. Ports A is not available in the 52-pin packagePLD INPUT BUS8INPUT MACROCELL &

uPSD3212A, uPSD3212C, uPSD3212CV108/163Decode PLD (DPLD)The DPLD, shown in Figure 55, is used for decod-ing the address for PSD MODULE and externalcom

109/163uPSD3212A, uPSD3212C, uPSD3212CVComplex PLD (CPLD)The CPLD can be used to implement system logicfunctions, such as loadable counters and shift

11/163uPSD3212A, uPSD3212C, uPSD3212CVP4.4 PWM1 25 I/O General I/O port pin8-bit Pulse Width Modulation output 1P4.5 PWM2 23 I/O General I/O port pin8

uPSD3212A, uPSD3212C, uPSD3212CV110/163Output Macrocell (OMC)Eight of the Output Macrocells (OMC) are con-nected to Ports A and B pins and are named a

111/163uPSD3212A, uPSD3212C, uPSD3212CVProduct Term AllocatorThe CPLD has a Product Term Allocator. PSDsoftuses the Product Term Allocator to borrow a

uPSD3212A, uPSD3212C, uPSD3212CV112/163The OMC Mask Register. There is one MaskRegister for each of the two groups of eight OutputMacrocells (OMC). Th

113/163uPSD3212A, uPSD3212C, uPSD3212CVI/O PORTS (PSD MODULE)There are four programmable I/O ports: Ports A, B,C, and D in the PSD MODULE. Each of the

uPSD3212A, uPSD3212C, uPSD3212CV114/163The Port pin’s tri-state output driver enable is con-trolled by a two input OR gate whose inputs comefrom the C

115/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 60. Peripheral I/O ModeTable 89. Port Operating ModesNote: 1. JTAG pins (TMS, TCK, TDI, TDO) are dedicat

uPSD3212A, uPSD3212C, uPSD3212CV116/163Port Configuration Registers (PCR)Each Port has a set of Port Configuration Regis-ters (PCR) used for configura

117/163uPSD3212A, uPSD3212C, uPSD3212CVPort Data RegistersThe Port Data Registers, shown in Table 97, areused by the MCU to write data to or read data

uPSD3212A, uPSD3212C, uPSD3212CV118/163Ports A and B – Functionality and StructurePorts A and B have similar functionality and struc-ture, as shown in

119/163uPSD3212A, uPSD3212C, uPSD3212CVPort C – Functionality and StructurePort C can be configured to perform one or moreof the following functions (

uPSD3212A, uPSD3212C, uPSD3212CV12/16352-PIN PACKAGE I/O PORTThe 52-pin package members of the uPSD321xDevices have the same port pins as those of the

uPSD3212A, uPSD3212C, uPSD3212CV120/163Port D – Functionality and StructurePort D has two I/O pins (only one pin, PD1, in the52-pin package). See Figu

121/163uPSD3212A, uPSD3212C, uPSD3212CVExternal Chip SelectThe CPLD also provides two External Chip Select(ECS1-ECS2) outputs on Port D pins that can

uPSD3212A, uPSD3212C, uPSD3212CV122/163POWER MANAGEMENTAll PSD MODULE offers configurable power sav-ing options. These options may be used individu-al

123/163uPSD3212A, uPSD3212C, uPSD3212CVThe PSD MODULE has a Turbo Bit in PMMR0.This bit can be set to turn the Turbo Mode off (thedefault is with Turb

uPSD3212A, uPSD3212C, uPSD3212CV124/163PLD Power ManagementThe power and speed of the PLDs are controlledby the Turbo Bit (Bit 3) in PMMR0 (see Table

125/163uPSD3212A, uPSD3212C, uPSD3212CVTable 100. Power Management Mode Registers PMMR2Note: The bits of this register are cleared to zero following P

uPSD3212A, uPSD3212C, uPSD3212CV126/163RESET TIMING AND DEVICE STATUS AT RESETUpon Power-up, the PSD MODULE requires a Re-set (RESET) pulse of duratio

127/163uPSD3212A, uPSD3212C, uPSD3212CVPROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACEThe JTAG Serial Interface pins (TMS, TCK, TDI,TDO) are de

uPSD3212A, uPSD3212C, uPSD3212CV128/163AC/DC PARAMETERSThese tables describe the AD and DC parametersof the uPSD321x Devices:➜ DC Electrical Specific

129/163uPSD3212A, uPSD3212C, uPSD3212CVTable 104. PSD MODULE Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off)ConditionsMCU Clock Frequen

13/163uPSD3212A, uPSD3212C, uPSD3212CVARCHITECTURE OVERVIEWMemory OrganizationThe uPSD321x Devices’s standard 8032 Core hasseparate 64KB address space

uPSD3212A, uPSD3212C, uPSD3212CV130/163MAXIMUM RATINGStressing the device above the rating listed in theAbsolute Maximum Ratings” table may cause per-

131/163uPSD3212A, uPSD3212C, uPSD3212CVEMC CHARACTERISTICSSusceptibility test are performed on a sample ba-sis during product characterization.Functio

uPSD3212A, uPSD3212C, uPSD3212CV132/163LU. 3 complementary static tests are required on10 parts to assess the latch-up performance. Asupply overvoltag

133/163uPSD3212A, uPSD3212C, uPSD3212CVDC AND AC PARAMETERSThis section summarizes the operating and mea-surement conditions, and the DC and AC charac

uPSD3212A, uPSD3212C, uPSD3212CV134/163Figure 70. Switching Waveforms – KeyWAVEFORMSINPUTS OUTPUTSSTEADY INPUTMAY CHANGE FROMHI TO LOMAY CHANGE FROM

135/163uPSD3212A, uPSD3212C, uPSD3212CVTable 113. Major ParametersParameters/Conditions/Comments5V TestConditions5.0V Value3.3V TestConditions3.3V Val

uPSD3212A, uPSD3212C, uPSD3212CV136/163Table 114. DC Characteristics (5V Devices)Symbol ParameterTest Condition(in addition to those in Table 109., pa

137/163uPSD3212A, uPSD3212C, uPSD3212CVNote: 1. IPD (Power-down Mode) is measured with:2. XTAL1=VSS; XTAL2=not connected; RESET=VCC; Port 0 =VCC; all

uPSD3212A, uPSD3212C, uPSD3212CV138/163Table 115. DC Characteristics (3V Devices)Symbol ParameterTest Condition(in addition to those in Table 110., pa

139/163uPSD3212A, uPSD3212C, uPSD3212CVNote: 1. IPD (Power-down Mode) is measured with:2. XTAL1=VSS; XTAL2=not connected; RESET=VCC; Port 0 =VCC; all

uPSD3212A, uPSD3212C, uPSD3212CV14/163RegistersThe 8032 has several registers; these are the Pro-gram Counter (PC), Accumulator (A), B Register(B), th

uPSD3212A, uPSD3212C, uPSD3212CV140/163Figure 71. External Program Memory READ CycleTable 116. External Program Memory AC Characteristics (with the 5V

141/163uPSD3212A, uPSD3212C, uPSD3212CVTable 117. External Program Memory AC Characteristics (with the 3V MCU Module)Note: 1. Conditions (in addition

uPSD3212A, uPSD3212C, uPSD3212CV142/163Figure 72. External Data Memory READ CycleTable 118. External Clock Drive (with the 5V MCU Module)Note: 1. Cond

143/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 73. External Data Memory WRITE CycleTable 120. External Data Memory AC Characteristics (with the 5V MCU

uPSD3212A, uPSD3212C, uPSD3212CV144/163Table 121. External Data Memory AC Characteristics (with the 3V MCU Module)Note: 1. Conditions (in addition to

145/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 74. Input to Output Disable / EnableTable 123. CPLD Combinatorial Timing (5V Devices)Note: 1. Fast Slew

uPSD3212A, uPSD3212C, uPSD3212CV146/163Figure 75. Synchronous Clock Mode Timing – PLDTable 125. CPLD Macrocell Synchronous Clock Mode Timing (5V Devic

147/163uPSD3212A, uPSD3212C, uPSD3212CVTable 126. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices)Note: 1. Fast Slew Rate output available on

uPSD3212A, uPSD3212C, uPSD3212CV148/163Table 127. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)Table 128. CPLD Macrocell Asynchronous Clo

149/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 78. Input Macrocell Timing (Product Term Clock)Table 129. Input Macrocell Timing (5V Devices)Note: 1. In

15/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 9. PSW (Program Status Word) RegisterProgram MemoryThe program memory consists of two Flash mem-ory: 64KB

uPSD3212A, uPSD3212C, uPSD3212CV150/163Table 131. Program, WRITE and Erase Times (5V Devices)Note: 1. Programmed to all zero before erase.2. The polli

151/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 79. Peripheral I/O READ TimingTable 133. Port A Peripheral Data Mode READ Timing (5V Devices)Note: 1. An

uPSD3212A, uPSD3212C, uPSD3212CV152/163Figure 80. Peripheral I/O WRITE TimingTable 135. Port A Peripheral Data Mode WRITE Timing (5V Devices)Note: 1.

153/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 81. Reset (RESET) TimingTable 137. Reset (RESET) Timing (5V Devices)Note: 1. Reset (RESET) does not rese

uPSD3212A, uPSD3212C, uPSD3212CV154/163Figure 82. ISC TimingTable 141. ISC Timing (5V Devices)Note: 1. For non-PLD Programming, Erase or in ISC By-pas

155/163uPSD3212A, uPSD3212C, uPSD3212CVTable 142. ISC Timing (3V Devices)Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.2. For Program

uPSD3212A, uPSD3212C, uPSD3212CV156/163Figure 85. External Clock CycleFigure 86. Recommended Oscillator CircuitsNote: C1, C2 = 30pF ± 10pF for crystal

157/163uPSD3212A, uPSD3212C, uPSD3212CVPACKAGE MECHANICAL INFORMATIONFigure 89. TQFP52 – 52-lead Plastic Thin, Quad, Flat Package OutlineNote: Drawing

uPSD3212A, uPSD3212C, uPSD3212CV158/163Table 144. TQFP52 – 52-lead Plastic Thin, Quad, Flat Package Mechanical DataSymbmm inchesTyp Min Max Typ Min Ma

159/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 90. TQFP80 – 80-lead Plastic Thin, Quad, Flat Package OutlineNote: Drawing is not to scale.QFP-ANdE1CPbe

uPSD3212A, uPSD3212C, uPSD3212CV16/163SFRThe SFRs can only be addressed directly in theaddress range from 80h to FFh. Table15., page 28 gives an overv

uPSD3212A, uPSD3212C, uPSD3212CV160/163Table 145. TQFP80 – 80-lead Plastic Thin, Quad, Flat Package Mechanical DataSymbmm inchesTyp Min Max Typ Min Ma

161/163uPSD3212A, uPSD3212C, uPSD3212CVPART NUMBERINGTable 146. Ordering Information SchemeFor other options, or for more information on any aspect of

uPSD3212A, uPSD3212C, uPSD3212CV162/163REVISION HISTORYTable 147. Document Revision HistoryDate Version Revision Details18-Dec-2002 1.0 First Issue04-

163/163uPSD3212A, uPSD3212C, uPSD3212CVInformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsib

17/163uPSD3212A, uPSD3212C, uPSD3212CV(3) Register addressing. The register banks,containing registers R0 through R7, can be ac-cessed by certain inst

uPSD3212A, uPSD3212C, uPSD3212CV18/163Table 4. Arithmetic InstructionsLogical InstructionsTable 5., page 19 shows list of uPSD321x Devic-es logical in

19/163uPSD3212A, uPSD3212C, uPSD3212CVTable 5. Logical InstructionsMnemonic OperationAddressing ModesDir. Ind. Reg. ImmANL A,<byte> A = A .AND.

uPSD3212A, uPSD3212C, uPSD3212CV2/163Table 1. Device SummaryPart NumberMax Clock(MHz)1st Flash(bytes)2nd Flash(bytes)SRAM(bytes)GPIO USB8032 BusVCC(V)

uPSD3212A, uPSD3212C, uPSD3212CV20/163Data TransfersInternal RAM. Table 6 shows the menu of in-structions that are available for moving dataaround wi

21/163uPSD3212A, uPSD3212C, uPSD3212CVFirst, pointers R1 and R0 are set up to point to thetwo bytes containing the last four BCD digits. Thena loop is

uPSD3212A, uPSD3212C, uPSD3212CV22/163External RAM. Table 10 shows a list of the DataTransfer instructions that access external DataMemory. Only indir

23/163uPSD3212A, uPSD3212C, uPSD3212CVBoolean InstructionsThe uPSD321x Devices contain a complete Bool-ean (single-bit) processor. One page of the int

uPSD3212A, uPSD3212C, uPSD3212CV24/163Jump InstructionsTable 13 shows the list of unconditional jump in-structions. The table lists a single “JMP add”

25/163uPSD3212A, uPSD3212C, uPSD3212CVTable 14 shows the list of conditional jumps avail-able to the uPSD321x Devices user. All of thesejumps specify

uPSD3212A, uPSD3212C, uPSD3212CV26/163Figure 14. State Sequence in uPSD321x DevicesOsc.(XTAL2)Read opcodeRead nextopcodeRead nextopcode anddiscardRead

27/163uPSD3212A, uPSD3212C, uPSD3212CVuPSD3200 HARDWARE DESCRIPTIONThe uPSD321x Devices has a modular architec-ture with two main functional modules:

uPSD3212A, uPSD3212C, uPSD3212CV28/163MCU MODULE DISCRIPTION This section provides a detail description of theMCU Module system functions and Peripher

29/163uPSD3212A, uPSD3212C, uPSD3212CVTable 16. List of all SFRSFR AddrReg NameBit Register NameReset ValueComments7654321080 P0 FF Port 0 81 SP 07 St

3/163uPSD3212A, uPSD3212C, uPSD3212CVTABLE OF CONTENTSFEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

uPSD3212A, uPSD3212C, uPSD3212CV30/163A4 PWM2 00PWM2 Output Duty CycleA5 PWM3 00PWM3 Output Duty CycleA6 WDRST 00Watch Dog ResetA7 IEA ES2EI2C00Interr

31/163uPSD3212A, uPSD3212C, uPSD3212CVD2 S2SETUP 00I2C (S2) Setup D4D5D6D7D8D9DADBDC S2CON CR2 EN1 STA STO ADDR AA CR1 CR0 00I2C Bus Control RegDD S2S

uPSD3212A, uPSD3212C, uPSD3212CV32/163Table 17. PSD Module Register Address OffsetCSIOPAddr OffsetRegister Name Bit Register NameReset ValueComments76

33/163uPSD3212A, uPSD3212C, uPSD3212CVNote: (Register address = csiop address + address offset; where csiop address is defined by user in PSDsoft)* in

uPSD3212A, uPSD3212C, uPSD3212CV34/163INTERRUPT SYSTEMThere are interrupt requests from 10 sources asfollows (see Figure 16., page 35). INT0 External

35/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 16. Interrupt SystemAI07427bINT0 USART Timer0 I2C INT1 Timer1 2nd USART Timer2 High Low Interrupt Polli

uPSD3212A, uPSD3212C, uPSD3212CV36/163USART Interrupt– The USART Interrupt is generated by RI (Receive Interrupt) OR TI (Transmit Interrupt).– When th

37/163uPSD3212A, uPSD3212C, uPSD3212CVTable 20. Description of the IE Bits.Table 21. Description of the IEA BitsTable 22. Description of the IP BitsBi

uPSD3212A, uPSD3212C, uPSD3212CV38/163Table 23. Description of the IPA BitsHow Interrupts are HandledThe interrupt flags are sampled at S5P2 of everym

39/163uPSD3212A, uPSD3212C, uPSD3212CVPOWER-SAVING MODETwo software selectable modes of reduced powerconsumption are implemented (see Table 25).Idle M

uPSD3212A, uPSD3212C, uPSD3212CV4/163Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

uPSD3212A, uPSD3212C, uPSD3212CV40/163Table 27. Description of the PCON BitsNote: 1. See the T2CON register for details of the flag descriptionI/O POR

41/163uPSD3212A, uPSD3212C, uPSD3212CVThe following SFR registers (Tables 29, 30, and31) are used to control the mapping of alternatefunctions onto th

uPSD3212A, uPSD3212C, uPSD3212CV42/163PORT Type and DescriptionFigure 17. PORT Type and Description (Part 1)AI07438Symbol Circuit Description In / O

43/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 18. PORT Type and Description (Part 2)AI07428bSymbol Circuit Function In/ Out PORT1 <3:0>, PORT3,

uPSD3212A, uPSD3212C, uPSD3212CV44/163OSCILLATORThe oscillator circuit of the uPSD321x Devices is asingle stage inverting amplifier in a Pierce oscill

45/163uPSD3212A, uPSD3212C, uPSD3212CVSUPERVISORYThere are four ways to invoke a reset and initializethe uPSD321x Devices. Via the external RESET pi

uPSD3212A, uPSD3212C, uPSD3212CV46/163WATCHDOG TIMERThe hardware Watchdog Timer (WDT) resets theuPSD321x Devices when it overflows. The WDT isintended

47/163uPSD3212A, uPSD3212C, uPSD3212CVWatchdog reset pulse width depends on the clockfrequency. The reset period is TfOSC x 12 x 222.The RESET pulse w

uPSD3212A, uPSD3212C, uPSD3212CV48/163TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2)The uPSD321x Devices has three 16-bit Timer/Counter registers: Time

49/163uPSD3212A, uPSD3212C, uPSD3212CVTable 39. Description of the TMOD BitsBit Symbol Timer Function7GateTimer 1Gating control when set. Timer/Counte

5/163uPSD3212A, uPSD3212C, uPSD3212CVIn-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

uPSD3212A, uPSD3212C, uPSD3212CV50/163Mode 0. Putting either Timer into Mode 0 makesit look like an 8048 Timer, which is an 8-bit Counterwith a divide

51/163uPSD3212A, uPSD3212C, uPSD3212CVMode 2. Mode 2 configures the Timer register asan 8-bit Counter (TL1) with automatic reload, asshown in Figure 2

uPSD3212A, uPSD3212C, uPSD3212CV52/163Table 41. Timer/Counter 2 Operating ModesNote: ↓ = falling edgeTable 42. Description of the T2CON BitsNote: 1. T

53/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 24. Timer 2 in Capture ModeFigure 25. Timer 2 in Auto-Reload ModeAI06625fOSCTF2CaptureTR2T2 pinControlTL2

uPSD3212A, uPSD3212C, uPSD3212CV54/163Mode 3. Timer 1 in Mode 3 simply holds its count.The effect is the same as setting TR1 = 0.Timer 0 in Mode 3 est

55/163uPSD3212A, uPSD3212C, uPSD3212CVSTANDARD SERIAL INTERFACE (UART)The uPSD321x Devices provides two standard8032 UART serial ports. The first port

uPSD3212A, uPSD3212C, uPSD3212CV56/163Serial Port Control RegisterThe serial port control and status register is theSpecial Function Register SCON (SC

57/163uPSD3212A, uPSD3212C, uPSD3212CVTable 44. Description of the SCON BitsBit Symbol Function7 SM0 (SM1,SM0)=(0,0): Shift Register. Baud rate = fOSC

uPSD3212A, uPSD3212C, uPSD3212CV58/163Baud Rates. The baud rate in Mode 0 is fixed:Mode 0 Baud Rate = fOSC / 12The baud rate in Mode 2 depends on the

59/163uPSD3212A, uPSD3212C, uPSD3212CVTable 45. Timer 1-Generated Commonly Used Baud RatesMore About Mode 0. Serial data enters and exitsthrough RxD.

uPSD3212A, uPSD3212C, uPSD3212CV6/163PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

uPSD3212A, uPSD3212C, uPSD3212CV60/163Figure 28. Serial Port Mode 0, WaveformsMore About Mode 1. Ten bits are transmitted(through TxD), or received (t

61/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 29. Serial Port Mode 1, Block DiagramFigure 30. Serial Port Mode 1, WaveformsAI06826Zero DetectorInternal

uPSD3212A, uPSD3212C, uPSD3212CV62/163More About Modes 2 and 3. Eleven bits aretransmitted (through TxD), or received (throughRxD): a Start Bit (0), 8

63/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 31. Serial Port Mode 2, Block DiagramFigure 32. Serial Port Mode 2, WaveformsAI06844Zero DetectorInternal

uPSD3212A, uPSD3212C, uPSD3212CV64/163Figure 33. Serial Port Mode 3, Block DiagramFigure 34. Serial Port Mode 3, WaveformsAI06846Zero DetectorInternal

65/163uPSD3212A, uPSD3212C, uPSD3212CVANALOG-TO-DIGITAL CONVERTOR (ADC)The analog to digital (A/D) converter allows con-version of an analog input to

uPSD3212A, uPSD3212C, uPSD3212CV66/163Table 46. ADC SFR Memory MapTable 47. Description of the ACON BitsTable 48. ADC Clock InputSFR AddrReg NameBit R

67/163uPSD3212A, uPSD3212C, uPSD3212CVPULSE WIDTH MODULATION (PWM)The PWM block has the following features: Four-channel, 8-bit PWM unit with 16-bit

uPSD3212A, uPSD3212C, uPSD3212CV68/163Figure 36. Four-Channel 8-bit PWM Block DiagramAI066478-bit PWM0-PWM3 Comparators Registers 8-bit PWM0-PWM3 Co

69/163uPSD3212A, uPSD3212C, uPSD3212CVTable 49. PWM SFR Memory MapPWMCON Register Bit Definition:– PWML = PWM 0-3 polarity control– PWMP = PWM 4 polar

7/163uPSD3212A, uPSD3212C, uPSD3212CVSUMMARY DESCRIPTIONThe uPSD321x Series combines a fast 8051-based microcontroller with a flexible memorystructure

uPSD3212A, uPSD3212C, uPSD3212CV70/163Programmable Period 8-bit PWMThe PWM 4 channel can be programmed to pro-vide a PWM output with variable pulse wi

71/163uPSD3212A, uPSD3212C, uPSD3212CVPWM 4 Channel OperationThe 16-bit Prescaler1 divides the input clock(fOSC/2) to the desired frequency, the resul

uPSD3212A, uPSD3212C, uPSD3212CV72/163I2C INTERFACEThe serial port supports the twin line I2C-bus, con-sisting of a data line (SDA1), and a clock line

73/163uPSD3212A, uPSD3212C, uPSD3212CVTable 51. Description of the S2CON BitsTable 52. Selection of the Serial Clock Frequency SCL in Master ModeBit S

uPSD3212A, uPSD3212C, uPSD3212CV74/163Serial Status Register (S2STA)S2STA is a “Read-only” register. The contents ofthis register may be used as a vec

75/163uPSD3212A, uPSD3212C, uPSD3212CVAddress Register (S2ADR)This 8-bit register may be loaded with the 7-bitslave address to which the controller wi

uPSD3212A, uPSD3212C, uPSD3212CV76/163USB HARDWAREThe characteristics of USB hardware are as fol-lows: Complies with the Universal Serial Bus specifi

77/163uPSD3212A, uPSD3212C, uPSD3212CVTable 62. USB Interrupt Enable Register (UIEN: 0E9h)Table 63. Description of the UIEN Bits76543210SUSPNDI RSTE R

uPSD3212A, uPSD3212C, uPSD3212CV78/163Table 64. USB Interrupt Status Register (UISTA: 0E8h)Table 65. Description of the UISTA Bits76543210SUSPND — RST

79/163uPSD3212A, uPSD3212C, uPSD3212CVTable 66. USB Endpoint0 Transmit Control Register (UCON0: 0EAh)Table 67. Description of the UCON0 Bits76543210TS

uPSD3212A, uPSD3212C, uPSD3212CV8/163Figure 3. TQFP52 ConnectionsNote: 1. Pull-up resistor required on pin 5 (2kΩ for 3V devices, 7.5kΩ for 5V devices

uPSD3212A, uPSD3212C, uPSD3212CV80/163Table 68. USB Endpoint1 (and 2) Transmit Control Register (UCON1: 0EBh)Table 69. Description of the UCON1 Bits76

81/163uPSD3212A, uPSD3212C, uPSD3212CVTable 70. USB Control Register (UCON2: 0ECh)Table 71. Description of the UCON2 BitsTable 72. USB Endpoint0 Statu

uPSD3212A, uPSD3212C, uPSD3212CV82/163The USCL 8-bit Prescaler Register for USB is atE1h. The USCL should be loaded with a value thatresults in a cloc

83/163uPSD3212A, uPSD3212C, uPSD3212CVTransceiverUSB Physical Layer Characteristics. The fol-lowing section describes the uPSD321x Devicescompliance t

uPSD3212A, uPSD3212C, uPSD3212CV84/163Table 78. Transceiver DC CharacteristicsNote: 1. VCC = 5V ± 10%; VSS = 0V; TA = 0 to 70°C.2. Level guaranteed fo

85/163uPSD3212A, uPSD3212C, uPSD3212CVReceiver CharacteristicsThe uPSD321x Devices has a differential input re-ceiver which is able to accept the USB

uPSD3212A, uPSD3212C, uPSD3212CV86/163External USB Pull-Up ResistorThe USB system specifies a pull-up resistor on theD- pin for low-speed peripherals.

87/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 44. Differential to EOP Transition Skew and EOP WidthFigure 45. Differential Data JitterAI06633Receiver E

uPSD3212A, uPSD3212C, uPSD3212CV88/163PSD MODULE The PSD Module provides configurable Program and Data memories to the 8032 CPU core (MCU). In additi

89/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 46. PSD MODULE Block DiagramBUSInterfaceWR_, RD_,PSEN_, ALE,RESET_,A0-A15D0 – D7CLKIN(PD1)CLKINCLKINPLDIN

9/163uPSD3212A, uPSD3212C, uPSD3212CVFigure 4. TQFP80 ConnectionsNote: 1. Pull-up resistor required on pin 8 (2kΩ for 3V devices, 7.5kΩ for 5V devices

uPSD3212A, uPSD3212C, uPSD3212CV90/163In-System Programming (ISP)Using the JTAG signals on Port C, the entire PSDMODULE device can be programmed or er

91/163uPSD3212A, uPSD3212C, uPSD3212CVDEVELOPMENT SYSTEMThe uPSD3200 is supported by PSDsoft, a Win-dows-based software development tool (Win-dows-95,

uPSD3212A, uPSD3212C, uPSD3212CV92/163PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSETTable 81 shows the offset addresses to the PSDMODULE registers

93/163uPSD3212A, uPSD3212C, uPSD3212CVPSD MODULE DETAILED OPERATIONAs shown in Figure 15., page 27, the PSD MOD-ULE consists of five major types of fu

uPSD3212A, uPSD3212C, uPSD3212CV94/163InstructionsAn instruction consists of a sequence of specificoperations. Each received byte is sequentially de-c

95/163uPSD3212A, uPSD3212C, uPSD3212CVTable 82. InstructionsNote: 1. All bus cycles are WRITE bus cycles, except the ones with the “Read” label2. All

uPSD3212A, uPSD3212C, uPSD3212CV96/163Power-down Instruction and Power-up ModePower-up Mode. The PSD MODULE internallogic is reset upon Power-up to th

97/163uPSD3212A, uPSD3212C, uPSD3212CVToggle Flag (DQ6). The Flash memory offers an-other way for determining when the Program cycleis completed. Duri

uPSD3212A, uPSD3212C, uPSD3212CV98/163Programming Flash MemoryFlash memory must be erased prior to being pro-grammed. A byte of Flash memory is erased

99/163uPSD3212A, uPSD3212C, uPSD3212CVData Toggle. Checking the Toggle Flag Bit(DQ6) is a method of determining whether a Pro-gram or Erase cycle is i